This invention relates to semiconductor manufacturing processes, and more particularly, to an improved system and method for finding the defective tools in a fabrication facility used in processing semiconductor wafers.
In order to produce a particular circuitry on a semiconductor wafer, the wafer has to pass through several processing steps. These processing steps involve depositing material layers and forming patterns on these material layers by photolithography, ion implantation, and thermal annealing, etc. Each of these processing steps must be performed perfectly on a wafer in order to produce functional circuitry. Each of the processing steps is monitored to detect for errors.
To ensure that the circuitry be fully functional, in-line testers conduct electrical and/or physical tests on the wafers after certain key process steps, and the test data is sent to various diagnostic tools to determine whether any errors occurred in that particular process. For example, after a series of implantation processes are performed, the wafer is examined to see if any defects have formed, or if the number of defects has exceeded a threshold level. If a defect is detected, or if the number of defects exceeds a threshold level, an operator adjusts the process immediately to ensure proper operation. After a wafer has gone through all the required processing steps, more comprehensive electrical and/or physical tests are then performed on each die on the wafer to ensure that the circuitry is functional. If defects are detected, then operators trace the processing history of the wafer and determine which process went wrong and generated the defects.
Methods have been developed in the past to determine the defective process. One method is the process-based commonality analysis. Because a semiconductor fab typically has several production lines running simultaneously, an operator may locate the defective process by finding a common process that all of the defective wafers have passed through. Suppose the wafers having high defective rates all went through a particular ion-implantation process, and wafers which did not go through that particular ion-implantation process had very few defects, then it is likely that the ion-implantation process is the source of the defects. By finding the common processes for which the defective wafers have gone through, the process-based commonality analysis provides a way of finding faulty processes.
One problem with such process-based commonality analysis is that each process may involve more than one tool. Moreover, each tool may be involved in more than one process. Thus, if a tool malfunctions, more than one process may be affected. By performing the process-based commonality analysis, an operator may determine that the defects come from more than one process. Subsequent efforts have to be spent to determine the exact cause of the defects. Moreover, a tool may have intermittent problems in which the tool functions normally during certain periods of time, but functions abnormally during other periods of time. Because the tool generates defects intermittently, sometimes the defects occur in one process while at other times the defects occur in another process. The process-based commonality analysis is likely to fail because no single process can be found to have processed all the defective wafers.
Thus, a more effective system and method of finding the cause of errors in the manufacturing process is desired.
A system and method for identifying a defective tool in a semiconductor fabrication facility is disclosed. The system includes an electrical parameter tester for identifying the defects on wafers, a failure signature analyzer for identifying a failure signature on the wafers having defects, a memory for storing a set of data representing the time period during which each wafer passed through each tool, and an equipment commonality analyzer for determining the tool that is mostly to likely to have caused the failure signature. The method includes the steps of processing wafers with the tools, generating a database containing information on the time period during which each wafer passed through each tool, determining the failure signature of the defective wafers, generating a lot list for each tool, assigning a weight value to each lot in the lot list, generate a cumulative value for each tool by sequentially adding the weight values of each lot in said lot list and keeping the cumulative value above or equal to zero, and assigning the tool with the largest maximum cumulative value as the tool most likely to have caused the failure signature.